nios2clock1_sopc

2011.08.20.10:43:01 Datasheet
Overview
  clk_0  nios2clock1_sopc
Processor
   cpu_0 Nios II 11.0
All Components
   cpu_0 altera_nios2 11.0
   onchip_memory2_0 altera_avalon_onchip_memory2 11.0
   jtag_uart_0 altera_avalon_jtag_uart 11.0
   sysid altera_avalon_sysid 11.0
   mypio32_0 mypio32 1.0
Memory Map
cpu_0
 instruction_master  data_master
  cpu_0
jtag_debug_module  0x00000800 0x00000800
  onchip_memory2_0
s1  0x00002000 0x00002000
  jtag_uart_0
avalon_jtag_slave  0x00000000
  sysid
control_slave  0x00000008
  mypio32_0
avalon_slave_0  0x00000010

clk_0

clock_source v11.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu_0

altera_nios2 v11.0
clk_0 clk   cpu_0
  clk
instruction_master   onchip_memory2_0
  s1
data_master  
  s1
data_master   jtag_uart_0
  avalon_jtag_slave
d_irq  
  irq
data_master   sysid
  control_slave
data_master   mypio32_0
  avalon_slave_0


Parameters

userDefinedSettings
tightlyCoupledInstructionMaster3MapParam
tightlyCoupledInstructionMaster3AddrWidth 1
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledDataMaster3MapParam
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster0AddrWidth 1
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave onchip_memory2_0.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 1
instSlaveMapParam <address-map><slave name='cpu_0.jtag_debug_module' start='0x800' end='0x1000' /><slave name='onchip_memory2_0.s1' start='0x2000' end='0x4000' /></address-map>
instAddrWidth 14
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_memory2_0.s1
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName Cyclone II
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='jtag_uart_0.avalon_jtag_slave' start='0x0' end='0x8' /><slave name='sysid.control_slave' start='0x8' end='0x10' /><slave name='mypio32_0.avalon_slave_0' start='0x10' end='0x18' /><slave name='cpu_0.jtag_debug_module' start='0x800' end='0x1000' /><slave name='onchip_memory2_0.s1' start='0x2000' end='0x4000' /></address-map>
dataAddrWidth 14
customInstSlavesSystemInfo <info/>
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave cpu_0.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x2020
RESET_ADDR 0x2000
BREAK_ADDR 0x820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 14
DATA_ADDR_WIDTH 14
NUM_OF_SHADOW_REG_SETS 0

onchip_memory2_0

altera_avalon_onchip_memory2 v11.0
clk_0 clk   onchip_memory2_0
  clk1
cpu_0 instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName onchip_memory2_0
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 8192
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 8192u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart_0

altera_avalon_jtag_uart v11.0
clk_0 clk   jtag_uart_0
  clk
cpu_0 data_master  
  avalon_jtag_slave
d_irq  
  irq


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

sysid

altera_avalon_sysid v11.0
clk_0 clk   sysid
  clk
cpu_0 data_master  
  control_slave


Parameters

id 0
timestamp 1313804571
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 0u
TIMESTAMP 1313804571u

mypio32_0

mypio32 v1.0
cpu_0 data_master   mypio32_0
  avalon_slave_0
clk_0 clk  
  clock_sink


Parameters

AUTO_CLOCK_SINK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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